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APR.15,1982SDE-2000SDE-2000 SERVICE NOTESAm25L04First EditionLow-Power.Twelve-Bit ApproximationLOGIC DIAORANS10SPECIFICATIONS·DIGITAL DELAY·gDE-2000InputLewelImpedance58k12OutputLevdl44 cBm [+18 dBm maxl into 6000 lgedCONNECTION DIAGRAM-20e8m【-8d8 m mexl into1ghas时Top ViewImpedanceFoedbeckSindLwl:t样m+18d8ma0pedanoe 10012RetumLavel +4 dBm +19 dBm maxImpedanee 7lkf2CV InModulation CVOperation Voltage to +10v V,allomablalmda"c■:民GeneralDalwy Time8830a1mphe regirtera contt of a set of marter lnshes that act n the由ntol clemen的in the dewie and char球ePerforan闭when the input clock is LOW,and s set of dave latches that hold the register data and change on the input clckDalwy Acturacy±0%LOW-Io HIGH.The dewioe aocepes data at the D input of the register and sends the data to theppropriate alrve的a好ooar at the re好e output land the D0 cutput)when the clock goes fromFrecueney Responu10H21o100H210 Ha to 16 kHz-3 dB at Deloy,0 to 320 msOW-10-HIG代the same time that data em tter bit the nestn口t bit is at to a LOW10H21e72Hu+0.5,-3B10e.0o40maroody foe the net iration.Te时f音reset by holding the55 artl signal L0 w during等ccdLOW-D-HIGH traraitian.The reghiter synchronouily eeiets to the stabe Q11 LOW,ind all the remaining registernals的6nRa0o00 dB,Direettpa相Gl,Th#CC IComerion Complta)agal h ahs t HIGH略thi time.After the cloc这gnd&outputB0 dB.DelyyHIGH resetting the register,the S signal is remoend.On the next clock LOW-co-HIGH trandtion the data anDynamig Range IIHF A)the D input is ast imto the Q1 1 regisor bit and the Q10 regber bit is t o a LOW ready for the next clockcycle.Dn the nast clock LOW-to-HIGH tranthtion data aneen the 10 megirter bit and o is iet to a low.This0e0oa移epeated for6ch时er bit in tumn until the regirter h屏b4nid,h5 the data9g3 s ato0Totl Hsmmonic Dstertiant ratad input&o.中uLess than 0.05%.Directthe CC signal goes LOW,and the regisoor is inhibited from further chenge until resat by o Start-ignal.Red 1 kHz008tp,02%m4关DiyPower27117V.30W220.2400ConsumptionDimensionsWeight65年12血RolandPrinted in Japan B-3 1
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